Inside the DS8700 Part 1 – POWER6

Power6 CPU

This is the first in a series of posts taking a behind-the-scenes look at the new DS8700.  Today, I’m taking a look at the POWER6 based processor complexes that make up the heart of the DS8700.

One of the strengths of the DS8000 platform is the use of IBM’s industry leading POWER Systems server technology as the foundation of the DS8000.  From the RS64 processors in the IBM ESS, to the POWER5 processors in the DS8100 and DS8300, to the POWER6 processors in the DS8700, having a fully integrated processor and memory subsystem has been key to delivering the highest levels of balanced throughput and performance in a disk subsystem.  The POWER6 processor has been a runaway hit in our server product line, and the DS8700 benefits from two years of real-world acceptance (and success!) as well as operational experience.  We’re also well positioned to take advantage of future advances in the POWER processor line without needing to make drastic changes to the fundamental architecture of the DS8000.

Here are some vital statistics of the DS8700 central electronics complexes, or CECs, as we like to call them.

• Dual IBM 4.7 GHz POWER6 based controllers, available with either 2 or 4 CPUs per controller.
• Up to 126 128 GB of system memory for cache and NVS available in the 2-way controllers.
• Up to 384 GB of system memory for cache and NVS available in the 4-way controllers.
• PCI Express Generation 2 internal I/O fabric (Covered in Part 2 of this series.)

In addition to the bigger/faster/stronger aspects of the move to POWER6, there are advances in server design that also come into play with the DS8700.  This is particularly true in the areas of Reliability, Availability, and Serviceability (RAS).  For example, each POWER6 processor has an internal processor recovery unit.  Before a machine instruction is dispatched to any of the POWER6’s nine(!) execution units, the recovery unit takes a snapshot of the processor state.  Should a fault be detected during the execution of that machine instruction, the processor state can be recovered and the instruction retried.  Should faults continue to be detected, we can use the recovery snapshot to re-create the processor state on another processor in the system, and execute the instruction there.  If necessary, the system can then dynamically de-allocate the failing components and schedule a support call all without affecting access to data!  In fact, IBM tortured tested this design by irradiating an operating POWER6 system with a high-energy proton beam while measuring the processor error recovery activities.  Shooting your DS8700 with a particle beam will void your warranty (and is certainly not recommended), but it’s nice to know that our engineers take their testing so seriously (and have access to seriously interesting test equipment.)

Before I forget… these new POWER6 resiliency features are in addition to Chipkill memory, redundant bit steering, spare cache lines, and advanced predictive failure analysis algorithms that have been carried forward from the DS8100 and DS8300.  All of this together  helps the DS8700 to deliver greater than five-nines availability.

So that’s a brief look at the new POWER6 processors in the DS8700.  Next, I’ll be taking a look at the new PCI-Express Generation 2 interconnect fabric in the DS8700.  Post timing will be dependent upon my workload as I’m a field guy with a large territory to support.

UPDATE:  Looks like we have a new DS8700 press release for your enjoyment.

Update 2:  Fixed a fat-finger error in the system memory size for 2-way controllers.